Ananya Nayak
CPU Verification Infrastructure Engineer @ NVIDIA
- Role
- Cpu Verification Infrastructure Engineer at NVIDIA
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
About Ananya Nayak
A highly motivated learner interested in optimizing hardware and software systems by pushing the boundaries of performance - I have experience in interfacing with microcontrollers with low memory/power requirements, with various interfaces such as BLE, and balancing power requirements while interfacing with accelerometers, gyroscopes and UART on the STM32L series of microcontrollers. Apart from embedded systems, I have also worked on ASIC design and at the System-on-Chip Extension Technologies [SoCET] team at Purdue University, I worked on formally verifying ASICs using SVAs. Currently, as a performance verification engineer at NVIDIA, I work on creating and testing performance scenarios to test various protocols, such as distributed virtual messaging, and analyzing latency and bandwidth for those setups. I am interested working in the design and verification of high performance architectures, and the optimizations that make high performance on low power possible.
Experience
Cpu Verification Infrastructure Engineer
Sep 2023 — Present
Education
Purdue University
Bachelor of Engineering
2016 — 2020
Pace Junior Science College
High School (Class XII)
Skills
- C
- Cloud Computing
- Java
- Microsoft Office
- Matlab
- C++
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