Anantha Krishnan A. K
Analog Design Methodology Engineer
- Role
- Analog Design Methodology Engineer at Intel
- Location
- Kollam, KL, IN
- LinkedIn followers
- 500 followers
About Anantha Krishnan A. K
Analog Reliability Verification Engineer with over 4 years of experience in advanced technology nodes including 5nm, 3nm, 1.8nm, and 1.6nm. Proven expertise in developing scalable CAD methodologies, executing transistor aging simulations, and supporting silicon-proven reliability sign-off. Experienced in Python scripting for automating Crossfire checks across multiple IP\'s, enabling efficient detection of design rule and connectivity issues through multiple validation layers. Skilled in integrating Machine Learning techniques to enhance reliability prediction and circuit robustness. Strong foundation in analog design fundamentals, statistical analysis, and reliability modeling.
Experience
Analog Design Methodology Engineer
Aug 2022 — Present · Bengaluru, IN
Education
Amrita Vishwa Vidyapeetham
Master of Technology - MTech, VLSI design
2020 — 2022
Cochin University of Science and Technology
Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering
2014 — 2018
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