Anand Gaurav

About Anand Gaurav

Strong enthusiasm for exploring the Digital VLSI field.* Strong grasp of Digital Design Fundamentals, ASIC design flow, Verilog and Digital IC Design along with Master of Technology in signal processing and communication.* Currently pursuing the final semester of Master of Technology in the Electrical Engineering Department at IIT Kanpur with a Cumulative Performance Index of 8.25 on a scale of 10.* Developed a 5-stage RISC MIPS processor with stages IF, ID, EX, MEM, and WB, and its testbench in Verilog HDL.* Designed a synchronous FIFO in Verilog.* Synthesized a Verilog code using Yosys as explained in projects section.* Completed a 2-month internship program in RTL Design where I designed an AHB to APB bridge using Verilog. Worked with Infosys Limited as a System Engineer for 18 months.Skill HDL* Basics of Physical Design*Hands-on experience of Cadence tool.*Communication Skills*RTL Design and verificationArea Of Interest Systems*Computer Organization and Architecture Always up for learning something new or collaborating on challenging ideas—let’s connect.

Experience

1. Hardware Engineer

   Qualcomm

   Jul 2025 — Present · Bengaluru, IN

   RTL Design and Verification

Education

• Indian Institute of Technology, Kanpur

  Master of Technology in Signal Processing and Communication

  2023 — 2025

• Maulana Abul Kalam Azad University of Technology, West Bengal (MAKAUT, WB)

  Bachelor of Technology in