Anandaselvan R
Lead Physical design @ Intel. ex- TI & ex- Cosmic circuit
- Role
- Physical Design Engineer at Intel
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
About Anandaselvan R
Seasoned Analog Layout Lead (15 years) and Physical Design Engineer with a combined expertise of 17 years in semiconductor design, with a proven track record of driving efficiency and innovation in project management. Experienced with layout of analog blocks such as ADC, DAC, PLL, bandgap, LDO, DC-DC boost, Class-D amplifiers, sense amp & IO buffers. Proficient in analog layout design methodologies with extensive experience in leading full-chip layout projects. Skilled in full-chip floor planning, placement, routing, and verification of analog and mixed-signal integrated circuits. Hands-on experience in 180nm to 6nm process nodes from foundries like Intel, Samsung, TI, TSMC, UMC, Fujitsu, NEC & Chartered and others. Skilled in Netlist-to-GDSII flow, timing closure, physical verification, and layout methodologies. Experienced in developing advanced scripts and leading cross-functional teams to success. Excellent problem-solving, communication, and collaboration skills. Passionate about contributing to competent projects that align with organizational goals. Recognized with \"Flawless Execution\" award by cosmic circuits and many otherrecognitionsthroughout my technical career.
Experience
Physical Design Engineer
Jan 2022 — Present · Bengaluru, IN
Education
NTTF
Diploma
2004 — 2007
Coventry University
Master of Science
2011 — 2014
Skills
- Vlsi
- Physical Design
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