Anand Pathak

About Anand Pathak

A senior level IC design engineer with extensive experience with strong architecture, design, synthesis, timing, design documentation and verification skills in the area of telecom/datacom/networking/SERDES (i.e. OTN, SONET, SDH, PDH, BPON, GPON, Ethernet, SERDES etc.) ASICs, FPGAs and System on the Chips (SOCs). Strong knowledge of front-end design tools and methodology used for multi-million gate count chip design. Experience with top level integration and management of multi-million gate count chip RTL releases.Experienced with various communication protocols and interfaces. Also experienced with various EDA tools and HDL and SW languages over the years- OTN, SONET/SDH, PDH, 10G/40G Ethernet, ATM, HDLC, BPON, GPON, SERDES- SFI-4 Phase 1, SFI-4 Phase 2, SFI-5.1, SFI5.2, SFI-5s, XFI, XAUI, RXAUI, XLAUI, OTL3.4, OTL3.8, STL256, HRMLD, Interlaken, MLIF, XLAUI, SPI-3, SPI-4 Phase 2, Utopia Level 2/3, POS- PHY Level 2/3- VCS, Questasim, Verilint, LEDA, Mentor 0in lint and CDC, SPYGLASS, Synopsys Design Compiler, Synopsys PrimeTime, Cadence RTL Compiler, Cadence Conformal (also with ECO option), Xemacs Auto Verilog, CVS, FPGA Express, Xilinx M1 series tools, Altera MAX-PLUS II, IBM Booledozer, ModelSim and Leonardo Spectrum- System-Verilog, Verilog-HDL, VHDL, PERL, TCL, C, Make, Assembly Language, SpecmanSpecialties- Architecture and Design of Complex Digital Circuits including design of Clocking, Clock Gating and Reset Circuit and Methodology- High Speed Digital Logic Design, RTL Coding and Synthesis, Top Level Chip Integration- Functional Verification and writing verification test plans- CDC design techniques and methodology, Lint, ECOs, Equivalence Checking, Developing Synthesis and Timing Constraints- Synthesis/Timing with multi-VT and dynamic clock gating options to optimize leakage power.

Experience

1. Senior Principal Design Engineer

   Broadcom

   Aug 2011 — Present

Education

• Motilal Nehru National Institute Of Technology

  Bachelor of Engineering, ECE

  1992 — 1996

Skills

• Logic Design
• Timing Closure
• Tcl
• Xilinx
• Systemverilog
• Vhdl
• Simulations
• Lint
• Hardware Architecture
• High Speed Design
• Low-Power Design
• Perl
• Eda
• Equivalence Checking
• Fpga
• Asic
• Debugging
• Ethernet
• Semiconductors
• Mixed Signal
• Cdc
• Static Timing Analysis
• Rtl Coding
• Architectural Design
• Verilog
• Rtl Design
• Serdes
• Cadence
• Ic
• Ecos
• Otn
• Modelsim
• Integrated Circuit Design
• Microprocessors
• Functional Verification
• Vlsi
• Soc
• High Speed Interfaces
• Logic Synthesis
• Specman