Anand Kumar Singh

About Anand Kumar Singh

Full ownership (RTL to GDS Implementation) of 2 timing critical partitions having timing critical cores like ARM Cortex M7 and timing critical IO protocols like quadspi and rgmii with more than 70 clocks in two successive tape outs in 40nm tech node. Currently owner of a 3rd partition having radar and fft component with more than 3.3 million instance count and extremely challenging in terms of congestion, timing and density. 3 times experience in full chip flat CLP signoff on SOCs based on 40nm, 16nm and 5nm tech nodes. Additional hands on experience on cleaning DRC and LVS of chip_top partition having wire bond based complex padring. Partition ownership gave hands on experience on Logical/Physical Synthesis, Floorplanning, Placement, CTS, Routing, DRC cleanup and RTL/Timing ECO implementation. Hands on experience on LEC cleanup of multiple partitions. Thorough knowledge of UPF and CPF and Full Chip Flat CLP signoff. Experience in resolving various Block level/chip_top level timing, Noise, Place and Roue, DRC, LVS, IR related issues. Hands on Experience on Cadence Genus, Innovus, Conformal Low Power and Synopsis Fusion Compiler.

Experience

1. Senior Physical Design Engineer

   Renesas Electronics

   Sep 2024 — Present · Noida, IN

Education

• Birla Institute of Technology, Mesra

  Bachelor of Engineering, Electrical and Electronics Engineering

  2014 — 2018

• Birla Institute of Technology and Science, Pilani

  Master in Engineering, Microelectronics

  2019 — 2021