Anagh Aditya
MSDV Engineer @Allegro MicroSystems | B.E. EEE ‘25 @BITS Pilani - Hyderabad Campus
- Role
- Mixed Signal Design Verification Engineer at Allegro MicroSystems
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Anagh Aditya
graduate with keen interests in VLSI Design and Computer Architecture. Also…
Experience
Mixed Signal Design Verification Engineer
Jul 2025 — Present · Hyderabad, IN
Education
Mother's Public School
Higher Secondary Certificate (CBSE)
2019 — 2021
Loyola School, Bhubaneswar
Secondary School Certificate (ICSE)
2008 — 2019
BITS Pilani, Hyderabad Campus
Bachelor of Engineering - BE
2021 — 2025
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