Ana Stefanovic

Experience

1. Senior Design Engineer

   Intel

   Jun 1999 — Present · Portland, OR, US

   20+ years of technical and leadership experience on multiple cutting-edge CPU and SoC projects, in all aspects of back-end design, from initial planning stages to final design sign off. Initial feasibility studies, placement and floorplanning, high-speed circuit design, static timing, noise, and power analysis and convergence; Interconnect design and global clock distribution. Particular focus and expertise in static timing analysis and integration, interconnect design and clock distribution. Led and coordinated teams of engineers in delivery of large, complex sections of microprocessor, with respect to design, floorplaning, timing verification and integration. Projects-• Mobile SoC: Broxton• iCore CPU: Broadwell, Crystalwell, Haswell, Westmere, Nehalem• Pentium 4 CPU: Prescott, Northwood, Willamette

Education

• Portland State University

  Master of Science (MS)

• Wine & Spirit Education Trust

  Diploma in Wines and Spirits (L4)

• University of Belgrade

  Structural Engineering

Skills

• Asic
• Verilog
• Processors
• Semiconductors
• Static Timing Analysis
• Vlsi
• Perl
• Logic Design
• Cmos
• Ic
• Wine
• Soc
• Systemverilog
• Microprocessors
• Application-Specific Integrated Circuits (Asic)
• Microarchitecture
• Wine Tasting
• Clock Distribution
• Rtl Design
• Low-Power Design
• Very-Large-Scale Integration (Vlsi)
• Circuit Design
• Physical Design
• System on a Chip (Soc)
• Timing Closure