Amul Desai
- Role
- Soc Engineering Manager at Intel
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Amul Desai
Over 9 years of design/verification experience with multiple successful project tapeouts.…
Experience
Soc Engineering Manager
Jul 2023 — Present
Skills
- Very-Large-Scale Integration (Vlsi)
- Ruby
- Systemverilog
- Cadence Virtuoso
- Modelsim
- Memory Design
- Sram
- Verilog-a
- Nand Flash
- Asic
- Low-Power Design
- Debugging
- Cadence
- Microprocessors
- Cmos
- Tcl
- High Speed Design
- Memory Test
- Eda
- C
- Mixed Signal
- Rtl Design
- Low Power Design
- Analog Circuit Design
- C++
- Vlsi Design
- System Verification
- Computer Architecture
- Circuit Design
- Static Timing Analysis
- Vlsi
- Integrated Circuit Design
- Eeprom
- Fpga
- Vhdl
- Embedded Systems
- Verilog
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