Amrut Jigajinni
Senior Design Engineer @Intel
Signup · Get unlimited contacts
WORK HISTORY
Senior Design Engineer @Intel
Bengaluru, IN
EDUCATION
Manipal Institute of Technology
MS, VLSI Design
Visvesvaraya Technological University
Bachelor of Engineering (B.E.), Electronics and Communications Engineering
SKILLS
ABOUT AMRUT JIGAJINNI
Masters in VLSI Design and around 3 years of experience in ASIC front end IP Design and Verification- Good Knowledge of Front End ASIC Design and Verification- Hands on experience in Implementing RTL and Verifying RTL modules using Bus Function Models(BFM\'s) in verilog- Expertise in analyzing the Spyglass CDC checks- Experience in writing Synthesis Design Constraints(SDC)- Experience in working on EDA tools such as VCS, Design Compiler, Spyglass CDC- Good Knowledge of Static Timing Analysis(STA)- Familiar with Shell scripting, PERL and basic TCLSpecialties:Digital Design, RTL implementation using Verilog HDL, Spyglass CDC, Synthesis, Verilog Test Bench.
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.