Amrit Chourasia

About Amrit Chourasia

Analog Design Engineer with 7.5+ years of experience, specializing in the design, analysis, and verification of high‑performance analog and mixed‑signal circuits. Since transitioning fully into Analog Design in August 2025, I have been focused on developing robust analog IPs across advanced technology nodes including 5nm.My hands‑on design work spans LDOs, current converters, oscillators, and MOS‑based bandgap references, supported by a strong understanding of device physics and high‑speed analog circuit behavior. I am proficient in industry‑standard design environments such as Cadence Virtuoso and Custom Compiler, with solid experience in schematic design, biasing, stability analysis, Monte Carlo, corner simulations, and layout‑aware verification.With an early foundation in SOC‑AMS verification (UVM, PG‑RTL, Verilog‑AMS, RNM), I bring a unique cross‑domain perspective that helps bridge design and verification requirements, ensuring first‑pass success and improved IP reliability.Passionate about analog innovation, I enjoy solving complex design challenges and contributing to next‑generation mixed‑signal solutions.

Experience

1. Senior Lead Analog Design Engineer

   恩智浦半导体

   Aug 2025 — Present · Noida, IN

Education

• BITS Pilani Work Integrated Learning Programmes

  Master of Technology - MTech, Microelectronics and VLSI

• CV Raman College of Engineering (CVRCE), Bhubaneswar

  Engineer’s Degree, Electrical, Electronics and Communications Engineering

  2013 — 2017