Amol Raghuwanshi

Mts Silicon Design Engineer @AMD

Bengaluru, KA, IN

EMAILS

[email protected]

MOBILE NUMBERS

+91 *********19

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WORK HISTORY

May 2022 — Present

Mts Silicon Design Engineer @AMD

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Bengaluru, IN

Working on next gen DDR LPDDR PHY

EDUCATION

1993 — 2005

Om Saints School

Seconary Education

2007 — 2011

Savitribai Phule Pune University

Bachelor of Engineering (BE), Electronics and Communication Engineering

SKILLS

Rtl CodingFunctional VerificationVerilogDigital ElectronicsApplication-Specific Integrated Circuits (Asic)Universal Verification Methodology (Uvm)Digital, Verilog,System Verilog,Ovm,UvmVery-Large-Scale Integration (Vlsi)Rtl DesignVlsiUvmAsicOpen Verification MethodologySystemverilog

ABOUT AMOL RAGHUWANSHI

12+ years of comprehensive experience in ASIC Verification domain - Technical Skills:HDL: Verilog HVL & Methodology: System Verilog, UVMProtocol : AXI4, APB, LPDDR5, DDR4 and DDR5 basics, I2C, JTAG, SMBUSRepository Tool : Perforce, GIT, SVN, CVSFamiliar with tools VCS, Verdi (Synopsys), NCSIM, SimVision (Cadence)Scripting: PythonGLS and Power aware simulationsOther Skills: Good at digital fundamentalsCoverage: Functional & code based Verification plan preparation IP and SubSystem level Verification

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