Amit Tejale

About Amit Tejale

Experienced in Physical Design/Verification Engineer with a demonstrated history of working in the VLSI industry- Successfully completed three months of hands on Physical Design Training at Qualcomm for 5nm technology- Skilled in DRC, LVS, SOFTCHECK, ERC, PERC, Antenna, PM, XOR, EM, IR drop- Worked on Innovus (encounter), ICC2/FC, Calibre Designrev, Genesys(Intel), ICV/ICWB (Synopsys) tools. Having experienced in analysis, debugging and fixing all the PV checks at 3/4/5/7/8/10/11/14nm- Strong engineering professional with a Master of Science (M.Sc.) focused in Electronic Science (VLSI) from Department of Electronic science (D.O.E.S.), Savitribai Phule Pune University.

Experience

1. Senior Lead Engineer

   Qualcomm

   Dec 2023 — Present · Bangalore Urban, IN

   Worked on floorplan at block level for TSMCN4. Recently worked as Project lead for 1st N4C-10LM technology and successfully delivered base/metal data before tapeout time for hard macros.

Education

• H.P.T. ARTS and R.Y.K. SCIENCE COLLEGE

  Bachelor of Science (B.Sc.), Electronic Science

  2010 — 2013

• Savitribai Phule Pune University

  Master of Science (M.Sc.), Electronic Science (VLSI)

  2013 — 2015

Skills

• Ltspice
• Standard Cell Layout
• Microsoft Excel
• Singing
• Microsoft Office
• Vlsi
• Verilog
• Pspice
• Linux
• Cadence Virtuoso Layout Editor
• Memory Layout
• Genesys
• Physical Verification
• Vhdl
• Microsoft Word
• Electronics
• Cadence Virtuoso
• Ic Validator
• Embedded Systems
• Tcl
• Physical Design
• Orcad Capture Cis
• Labview