Amit Srivastava

About Amit Srivastava

I have around 23+ years of extensive experience in front end verification which includes constrained random (UVM, System Verilog and System C with PSL and SVA) and directed verification using Verilog and C in VLSI domain. I have in depth experience in verification of complex SOCs (ARM, MIPS, DSP based) and complex IPs like Ethernet, Memory controllers plus extensive experience in DDR/LPDDR, AMBA AXI/AHB/APB, OCP etc protocols. Specialties: VirtualizationAIUVMVerilogSystemVerlogSystemCARM based SOC verificationIP verificationAMBA AHB/AXI, OCP, I2C/SPIMemory controller, DDR, EthernetScriptingPeople management

Experience

1. Senior Staff Manager

   Marvell Technology

   Jun 2022 — Present · Bengaluru, IN

   Working on virtualization concepts and using them for h/w resources (co-preocessors) optimization. Developing VIP to verify the design features. Mentoring the team.

Education

• Madan Mohan Malaviya University of Technology

  BE, Electronics & Communication

  1997 — 2001

Skills

• Dft
• Soc
• C
• Vlsi
• Systemverilog
• Scripting
• System on a Chip (Soc)
• Application-Specific Integrated Circuits (Asic)
• Assertions
• Uvm
• Eda
• Rtl Design
• Arm Cortex-M
• Functional Verification
• Arm
• Debugging
• Systemc
• Very-Large-Scale Integration (Vlsi)
• Digital Signal Processors
• Verilog
• Asic
• Ethernet