Amit Roy
R&D Engineer | RTL Design | Product Validation | VLSI Enthusiastic | Design Engineer | Formal/Equivalence Verification Specialist | RTL-to-GDS Signoff Expert
- Role
- Design Engineer at Tech Mahindra
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
About Amit Roy
Design Engineer | Formal/Equivalence Verification Specialist | RTL-to-GDS Signoff…
Experience
Design Engineer
Apr 2025 — Present · Bengaluru, IN
My current focus is on Formal Equivalence Verification (FEV) for complex SoC designs, where I’ve owned and executed FEV for 20+ partitions—spanning sections, super sections, and full-chip validation. I work with advanced EDA tools like Formality, Fusion Compiler, and VCLP, using Perforce for version control in the Cheetah flow. Core Expertise:• Formal Equivalence Verification (FEV) – RTL & Netlist• RTL Design – Synthesis/Non-Synthesis• EDA Tools: Formality, Fusion Compiler, VCLP• Debugging & Constraint Management• DesignWare IP Integration• ECO Handling & Scan Logic Modification
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