Amit Kumar Bharti

About Amit Kumar Bharti

Expertise in Developing UVM/OVM System Verilog based testbench from scratch Skilled at Developing Testplan, Testcase, Track and Debug bugs in Design Experience in writing and analysis of Coverage and Assertion in System Verilog Experience in IP blocks implementation(RTL Design) using VHDL and Verilog Experience in Ultra Low Power & Generic Design Development Experience in Developing of Design Specification, Micro Architecture & Integration Guide Experience in Developing SystemC TLM model Communication IP’s protocol like SPI, I2C, USB2.0,USB 3.0 and BLE Controller Good Experience of AXI3 & Wishbone SoC Bus Good Design Experience of IP’s like GFSK Modem, CRC16, RAM Controller Strong understanding of digital design Exposure to STA, Synthesis, Lint Check & LEC

Experience

1. R & d Engineer Ic Design 4

   Broadcom

   Nov 2022 — Present · Bengaluru, IN

Education

• IDEAL INSTITUE OF TECHNOLOGY

  B.TECH, Electronics and Communications Engineering

  2007 — 2011

• BITS Pilani Work Integrated Learning Programmes

  Master of Technology - MTech, Microelectronics

Skills

• Rtl Coding
• Fpga
• Asic
• Gls
• Perl
• Eda
• System Verilog
• Tcl
• Uvm
• Verilog/Vhdl
• Systemverilog
• Matlab
• Functional Verification
• Systemc
• Integrated Circuit Design
• Microprocessors
• Soc
• C/C++
• Unix/Linux
• Verilog
• Vlsi
• Vhdl
• Lint
• Rtl Design
• Ncsim
• Static Timing Analysis
• Modelsim
• C
• Cdc
• Unix Shell Scripting