Amit Duggal

About Amit Duggal

19+ Years of VLSI experience in building Best in class chips. Expertise knowledge in the domain of RTL design, Auto Safety ASIL designs, Logical Synthesis, Physical Synthesis, Static Timing Analysis(STA) closure for block level as well chip level, Formal verification, Functional ECOs implementation, Low power checks with UPF, RTL integration, RTL checks.

Experience

1. Principal Engineer Manager

   Qualcomm

   Dec 2022 — Present

Education

• Thapar Institute of Engineering & Technology

  Bachelor of Engineering (B.E.), Electronics and Communications Engineering

  2002 — 2006

Skills

• Rtl Coding
• Timing
• Processors
• Low-Power Design
• Arm
• Dft
• Very-Large-Scale Integration (Vlsi)
• Drc
• Logic Synthesis
• Eco
• Systemverilog
• Static Timing Analysis
• Ncsim
• Physical Design
• Eda
• Usb
• Logic Design
• Formal Verification
• Vlsi
• Asic
• Verilog
• Floorplanning
• Integrated Circuit Design
• Rtl Design
• Amba Ahb
• Tcl
• Soc
• Primetime
• Signal Integrity
• Modelsim
• Low Power Design
• Timing Closure
• Lvs
• Functional Verification
• Jtag
• Debugging
• Physical Verification