Amit Dudeja

About Amit Dudeja

Around 16 years of rich experience in Semiconductor, EDA and Software industries, majorly in the domain of System Level (ESL) design, development and verification.Having experience of performance and power modeling for architecture exploration use case using SystemC and TLM2.0. Also worked on AI workload modelling for architectural exploration.Built and leading the team of engineers working on SystemC simulation flows of AMD FPGA. System Standard: SystemC/TLM2.0Programming Languages : C, C++, Data Structures & AlgorithmsHardware Description Languages: Verilog, VHDL, SystemVerilog Verification Methodology: UVMScripting Language: Tcl, Power Standard: UPF3.0Bus Protocols: HBM,DDR,LPDDR,AXI, Tensilica PIF Protocol Tools: Synopsys PA tools for architecture exploration (PA-MCO & PA-Ultra), TLMC,Xilinx Vivado

Experience

1. Smts Design Engineer Manager

   AMD

   Jul 2024 — Present · Hyderabad, IN

   Built and Leading the team of 15 engineers- Working on enabling SystemC simulation flow of AMD FPGA- Performance Modelling of memory controllers, pcie controller and interconnect

Education

• Bharati Vidyapeeth

  B.Tech, Electronics and Communication

  2005 — 2009

Skills

• Arm
• Perl
• Embedded Systems
• C++
• Tcl
• Device Drivers
• Systemc
• Unix
• Algorithms
• Linux
• Debugging
• Data Structures
• Upf
• Power Analysis
• Software Development
• Shell Scripting
• Arm Architecture
• C
• Programming