Amit Agarwal

Principal Design Engineer Manager @Satixfy

Farnborough, GB

Working as an architect of second-generation Digital Beam forming chip for phased array antenna• Responsible for translating product requirement into the chip architecture keeping product simplification in mind. • Responsible for breaking the high-level design into micro architecture keeping the layout of the chip and interconnectivity in mind.• Reviewing the low-level design and implementation with the team to assure it’s aligned with the high-level architecture design.• Working closely with the verification and implemtation team to deliver high quality, power, area and performance. • Responsible for delivering SOC as per the timelines. • Reviewing and closing the back-end implementation issues.• Responsible for chip lab bring up plan development and execution.• Responsible for defining, effort estimatation and tracking of the work• Acting as a Manager for small Engineering team.