Amirali Ghofrani
Design Manager | Design Lead | Hardware Design Engineer at Google TPU
- Role
- Design Manager at Google
- Location
- San Diego, CA, US
- LinkedIn followers
- 500 followers
About Amirali Ghofrani
Specialties: Hardware Design, ASIC/FPGA, SystemVerilog/Verilog/VHDL, GPU, Memristor reliability
Experience
Design Manager
Feb 2024 — Present · San Diego, CA, US
Education
UC Santa Barbara
Master of Science (M.Sc.), Computer Engineering
2010 — 2013
University of Tehran
Bachelor of Science (B.Sc.), Computer Engineering
2002 — 2007
UC Santa Barbara
Doctor of Philosophy (Ph.D.), Computer Engineering
2010 — 2016
University of Tehran
Master of Science (M.Sc.), Computer Engineering
2007 — 2010
Skills
- Spice
- Functional Verification
- Systemc
- Field-Programmable Gate Arrays (Fpga)
- Eclipse
- Matlab
- Dft
- Circuit Design
- Linux
- Modelsim
- Debugging
- Data Structures
- Algorithms
- Stratus
- Verilog
- Fpga
- Non-Volatile Memory
- Vhdl
- Simulations
- Reram Variation
- Altera Quartus
- Digital Design
- Xilinx
- Integrated Circuit Design
- Microprocessors
- Signal Processing
- C++
- High Level Synthesis
- Reram Reliability
- Java
- Tcl
- Testing
- C
- Latex
- Computer Architecture
- Cadence Virtuoso
- Simulation
- Microcontrollers
- Memristors
- Numerical Simulation
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