Ameya Patil

Staff Digital Design Engineer @Iq-Analog Corporation

Working on sub system RTL design, top level integration and functional verification (module level and SoC level) of custom feature DSP IP cores and full chip processor based SoCs for high speed configurable data converter ASICs. Also concentrate on Lint, DFT/ATPG vector gen, Burn-in, logic synthesis, LEC, constraints development and STA to meet timing and coverage requirements.