Ameena Musthafa
RTL Design Verification Engineer | SV | UVM | VCS | SoC | IP
- Role
- Vlsi Design Verification Engineer at Wipro
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Ameena Musthafa
Completed my graduation in Electronics Engineering and had a focused training as a design verification Engineer in UVM by Wipro. Good knowledge on SV, UVM. Experienced in using different verification tools like DVE and Verdi. Attended additional training on different scripting languages and still exploring. Worked for Verification of RTL design for #*XP_semiconductors Projects including 5G. Currently working with #*tel_Corporation Graphics team in Verification of RTL Design. IP/SoC Verification.
Experience
Vlsi Design Verification Engineer
Jun 2019 — Present
VLSI Design Verification engineer with strong knowledge in UVM, SystemVerilog SV. Knowledge in UVM testbench development, testcase coding and debugging, testplan development, functional and code coverage.Worked for Verification of RTL design for *XP semiconductors Projects including 5G. Working with In**l Graphics team in Verification of RTL Design. Handling IP specific works.
Education
College of Engineering, Poonjar-Kottayam
Bachelor of Technology - BTech, Electronics and Communication Engineering
2015 — 2019
Christava Mahilalayam Higher Secondary School
SSLC, Kerala State
2000 — 2013
SNDP HSS-Aluva
Higher Secondary-+2, Computer Science
2013 — 2015
APJ Abdul Kalam Technological University
Bachelor of Technology - BTech, Electronics and Communications Engineering
2015 — 2019
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