Amar Yadav

About Amar Yadav

Seasoned Associate Director with extensive experience of 18 years in PDK development andqualification along with automation and CAD. Expert in physical verification (DRC, LVS), parasiticextraction, PCell, EDA applications, productivity enhancement flow development, and simulation.Actively supporting team to create complex, multi-model linked CAD networks using parameter andformula-based construction allowing for quick, robust updates as the design evolves. An enthusiasticprofessional with the aptitude to work within a dynamic engineering team or the capability todeliver a project independently.

Experience

1. Associate Director

   Samsung Semiconductor

   Mar 2022 — Present · Bengaluru, IN

   Managing a team of highly motivated engineers to perform PDK PEX (parasitic extraction)component development and UnitQA of all Samsung PDKs including SOC- GAA, FinFet, CMOS, FDSOI,RF, SOI, DDI-Display, CIS-Sensor, BiCMOS, HV, NVM, BCD etc technologies. Developing and driving acoherent Design Enablement EDA strategy to meet the needs of Process Design Kits and Design-Technology Co-optimization on next-generation process technology nodes. Serving as the centralDesign Enablement contact for both tactical and strategic EDA issues. Identify agendas and concisekey messages to achieve Design Enablement strategic directions through executive decisions. Teerdevelopment team to standardize development methodology to optimize effectiveness. Closecollaboration with EDA vendors to validate PEX tools and improve PEX tool accuracy and usability.CAD flow for Analog/Mix signal Design, PDK, iPDK, Spice simulation, PCells, CDF, Callbacks, techfiles,DRC, ERC, Multiple-patterning, LVS, DFM, post-layout extraction, Metal fill, Layout Finishing & CADtool development. Collaborating with EDA vendors to enable new design capabilities for PDK.Develop and support parasitic extraction flow (StarRC/Quantus/xRC/xACT) to internal and externalcustomers. Maintaining and customizing design kits and CAD infra-structure onSynopsys/Cadence/Mentor platforms for various process nodes. Driving PDK quality by developingand synthesizing good quality test cases for better coverage. Managing dynamic PDK roadmap andontime delivery by providing proper sizing and effectively communicating progress and expectationswith team members and stakeholders. Pro-eKcient in writing parasitic extraction deck (ITF-StarRC,MIPT-xRC/xACT, ICT-Quantus, PEX map files for model-pex boundary etc). Pro-eKcient in PEX deckaccuracy checks, BEOL, MOL, VIAs and Device accuracy analysis. Pro-efficient in pcell (parameterizedcells), fluid pcells, FGR PCells development, CDF generation, callbacks & ppf creations.

Education

• St. Margaret Engineering College, University of Rajasthan

  Bachelor's, Electronics & Communication Engineering

  2003 — 2007

• University of Rajasthan

  B.E., Electronics and Communication Engg

  2003 — 2007

Skills

• Eda
• Semiconductors
• Cadence Skill
• Analog Circuit Design
• Mixed Signal
• Virtuoso
• Asic
• Pll
• Drc
• Simulations
• Application-Specific Integrated Circuits (Asic)
• Very-Large-Scale Integration (Vlsi)
• Electronics
• Layout Versus Schematic (Lvs)
• Design Rule Checking (Drc)
• Analog
• Lvs
• Pcell
• Cadence
• Soc
• Rf
• Cadence Virtuoso
• Cmos
• Vlsi