Amartya Singh
SoC Design Engineer @ Intel | MTech - VLSI @ Nirma University
- Role
- Cpu Physical Design Timing Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Amartya Singh
I am a Graduate Engineering Trainee at Intel Corporation, where I apply my domain expertise in ASIC Design and Power Optimization to semiconductor projects. As an intern, I have contributed to the development and validation of various SoC components and systems, using tools such as TCL and Hardware Engineering. I have also collaborated with senior engineers and researchers to learn from their insights and feedback and to deliver high-quality results within tight deadlines.In addition to my practical experience, I am a final-year postgraduate student in VLSI at Nirma University, with a strong academic background in Electronic and Communications Engineering Technology. I have completed multiple certifications in Python and Data Structures, enhancing my programming and analytical skills. I am also a Student Placement Coordinator and a Teaching Assistant at my university, demonstrating my leadership and communication abilities. I am passionate about learning new technologies and exploring the intersection of academia and industry, constantly seeking opportunities to apply theoretical insights to real-world challenges. My goal is to make significant contributions to the ever-evolving landscape of VLSI technology.
Experience
Cpu Physical Design Timing Engineer
Jun 2024 — Present · Bengaluru, IN
Education
Kendriya Vidyalaya
12th Science PCM, Computer Science
Kendriya Vidyalaya
10th
Gujarat Technological University (GTU)
Bachelor of Engineering - BE, Electronic and Communications Engineering Technology
Nirma University
Master of Technology - MTech, VLSI DESIGN
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