Amarnath Mahadevuni

About Amarnath Mahadevuni

Experienced in Design Verification in the following areas: a) Translating hardware…

Experience

1. Senior Design Verification Engineer

   NVIDIA

   Jul 2018 — Present

   Assumed ownership of multiple tasks that contribute to verification of NVIDIA GPU hardware memory subsystem. Analyzed testbench infrastructure requirements and spearheaded the verification task progress for the features owned. Developed constrained-random stimulus for a subset of features for the verification of GPU memory subsystem using C++. Added new memory request interfaces using verilog for the features owned in the test-bench. Updated, enhanced and maintained an internal C++ library to manage process address space mapping within the GPU. Triaged and debugged several failures in test-suite regression runs successfully.

Skills

• C
• Field-Programmable Gate Arrays (Fpga)
• Static Timing Analysis
• Systemverilog
• Specman E
• Linux
• Very-Large-Scale Integration (Vlsi)
• C++
• Cadence Spectre
• Matlab
• Asic Design and Verification
• Uvm
• Verilog Rtl Design
• Fpga
• Universal Verification Methodology (Uvm)
• Eda
• Spice