Alpesh Goyal

About Alpesh Goyal

3 years of industry experience in the field of SoC frontend design and implementation flow. Have performed formal equivalence checking, developed the detailed clock structure of complete SoC for writing synthesis constraints and have done Spyglass CDC analysis.Developed synthesis constraints and done details timing analysis of full SoC.Specialties: Logic Equivalence Check, CDC, Synthesis, Timing Analysis, Constraint development

Experience

1. Senior Staff Engineer

   Qualcomm

   Dec 2023 — Present

Education

• Lakshmi Narain College of Technology

  BE, Electronics and Communication Engineering

  2006 — 2010

• International Institute of Information Technology Hyderabad (IIITH)

  M.tech, Microelectronics and VLSI design

  2010 — 2012

Skills

• Cadence
• Soc
• Arm
• C
• Dft
• Digital Design
• Functional Verification
• Physical Design
• Xilinx
• Systemverilog
• Cadence Virtuoso
• Vlsi
• Static Timing Analysis
• Digital Electronics
• Logic Synthesis
• Timing Closure
• Debugging
• Rtl Design
• Fpga
• Asic
• Integrated Circuit Design
• Microprocessors
• Verilog
• Cmos
• Vhdl
• Perl
• Eda
• Modelsim
• Rtos
• Tcl
• Formal Verification
• Spyglass