Alok Nandini Roy
Semiconductor Technologist | Project & Strategy Management | DTCO | Emerging & Pathfinding Research Initiatives
- Role
- Technologist, Pathfinding and Technology Engineering at Intel
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Alok Nandini Roy
With my two decades of career in leading, managing, training and hands-on engineering experience in design, device, process, products and product development support interface (such as Industrial, Automotive, Healthcare, Communications, Consumer and Computing Product) I am confident that I can manage and drive your project to excellence.My email ID: a••••••••@gmail.comSOFT SKILL SETS: Excellent leadership and communication skills, an effective communicator, able to clearly articulate ideas and inspire others for action,\'Self-starter\' attitude, motivated, dynamic, creative and result-oriented and the ability to make decisions independently, Passionate, highly collaborative, an end to end thinker, able to influence and drive change across teams Top 10 Technical Expertise / Skill-sets in my ~ 20yrs of Semiconductor Industry Career: 1. Total Cost of Ownership (TCO), Program Management, and Solution Engineering2. Process Development, Technology Engineering & Design Technology Co-Optimization (DTCO)3. Emerging Technology & Path-finding Initiatives 4. PPA (Power-Performance-Area) Scaling, Technology Definition & Benchmarking for Non-Volatile Flash-Memory and FPGA products5. SPICE Modeling, TCAD Modeling, Device Design, Product Development, Testing & Characterization, Reliability6. CAD Tool, Mask Design & Layout, Verification, Design & Flow7. Test chip & Test Structure Development, Electrostatic Discharge (ESD) Protection & Latch Up Prevention 8. Fabrication (Wafer fab) Equipment, Physics, Engineering, Characterization & Metrology Tools9. Failure Analysis, Quality and Reliability, Electrical and Thermo-mechanical. IC/Semiconductor Packaging, Package Assembly, Silicon back-end, LGA, BGA, and PGA.
Experience
Technologist, Pathfinding and Technology Engineering
Dec 2016 — Present
Design Technology Co-Optimization (DTCO)Layout OptimizationTechnology Architecture Co-Optimization Power/Performance/Area (PPA) OptimizationModel development, Benchmarking and Test Chips Emerging Technology & Path-finding Initiatives
Education
University at Albany
Ph.D, Physics
1999 — 2002
University at Albany
MS, Solid State Physics
1997 — 1999
Skills
- Spice
- Mask Design
- Debugging
- Metrology
- Silicon
- Esd
- Flash Memory
- Cadence Virtuoso
- Characterization
- Simulations
- Testing
- Tcad Process Simulation
- Process Integration
- Integrated Circuit Design
- Microprocessors
- Drc
- Calibration
- Failure Analysis
- Sentaurus
- Optics
- Device Characterization
- Semiconductor Industry
- Cmos
- Integrated Circuits (Ic)
- Test Chip
- Ic
- Laboratory Documentation
- Research
- Semiconductors
- Semiconductor Device
- Latch Up
- Device Modeling
- Laboratory Audits
- Mixed Signal
- Physics
- Tcad Dc and Thermo Electric Mixed Mode Transient Simulation
- Product Engineering
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