Alok Jadhav
- Role
- Senior Design Verification Engineer at Intel
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Alok Jadhav
To secure a challenging position where I can effectively contribute my skills as an…
Experience
Senior Design Verification Engineer
Aug 2015 — Present
Pre-Silicon Logic Verification of Front end design Features in Complex IPs and SoCs.
Skills
- Engineering
- Front-End Design
- Microsoft Office
- Tcl
- Java
- Embedded Systems
- Integrated Circuit Design
- Field-Programmable Gate Arrays (Fpga)
- Asic
- Digital Electronics
- Functional Verification
- Electronics
- Embedded Software
- Image Processing
- Physical Design
- Perl Script
- Modelsim
- Eclipse
- Javascript
- Xilinx Ise
- C
- Uvm
- Back-End
- Application-Specific Integrated Circuits (Asic)
- C++
- Analog Circuit Design
- Team Leadership
- System Verilog
- Linux
- Programming
- Ovm
- Silvaco
- Systemverilog
- Perl
- Very-Large-Scale Integration (Vlsi)
- Verilog
- Fpga
- Cadence Virtuoso
- Vlsi
- Altera Quartus
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.