Yun-Rong du
ASIC Design Engineer Intern @Ambarella | MSEE @Columbia University
- Role
- Asic Design Engineer Intern at Ambarella Inc
- Location
- New York, NY, US
- LinkedIn followers
- 500 followers
About Yun-Rong du
Open to opportunities in RTL design and verification. I’m a graduate student at Columbia University pursuing an M.S. in Electrical Engineering, with a strong foundation in digital IC design and computer architecture. My academic and project work spans RTL design, ASIC/FPGA development, and full tapeout flows. Outside the lab, as a FIRST Alumni, you’ll probably find me volunteering or mentoring students at FIRST Robotics Competition.🤖
Experience
Asic Design Engineer Intern
Jun 2025 — Present · Santa Clara, CA, US
In Progress) Integrating absolute value comparison into the min-max pooling module and restructuring pipeline stages for area reduction- Developed an internal Perl-based tool to explore optimal memory configurations based on size and port specifications with Samsung memory compiler; helped increase search efficiency by over 50% with memory usage
Education
National Taiwan University
Bachelor's degree
2020 — 2024
Columbia University
Master's degree
2024 — 2025
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