Alexey Afanasyev

About Alexey Afanasyev

SOC/ASIC/IP design and validation in simulation, emulation and FPGA. 20 years hands-on…

Experience

1. Soc Design Engineer

   Intel

   Jan 2013 — Present

   Multi vendor emulation models development for server, IO, desktop and laptop SOC with graphics (GPU). Enabled and maintained infrastructure for continues development and integration of big box emulation models (100+ FPGAs) for multiple server products and educated multiple teams on how to use it. Maintained build flow and test environment (TE) to release FPGA / emulation models on cadence. Enabled in emulation DDR5/4 and LPDDR5/4 interfaces and maintained memory subsystem including BIOS MRC Python test bench with unit tests. Power management and memory transactors, trackers, Simics virtual platform. Remodeled ASIC RTL (System Verilog), FW (C/C++) for deployment on FPGA / emulation. FPGA Atom SOC prototyping for full range of 14 nm Atom SOCs mobile devices (from phones to tablets) on Xilinx FPGAs. Supported junior engineers and customers to perform HW/FW/SW pre-silicon co-verification on emulation models.

Education

• Moscow Institute of Physics and Technology (State University) (MIPT)

  Master of Science