Alex Odishvili

About Alex Odishvili

Get Technical manager IC designer position. Get more responsibility in IC design…

Experience

1. Lead Eo Ir Soc Roic Designer

   L3Harris Technologies

   Jan 2021 — Present · Tempe, AZ, US

   designing 8um pitch 8Kx6K iR LWIR ROIC\\\\ndesigned CDS column ADC\\\\ndesigned analog ROIC Library in Skywater 90nm CMOS process.\\\\nWon L3Harris call for idea competition with proposal 3D DROIC with enhanced performance\\\\nWrote white paper : ROIC enhancement main 3 directions.Technological guidelines and design initiatives.\\\\nVerified in QuestaSim using System Verilog\\\\nand in cadence hierahy editor Verilog and Spectre following ROIC designs: Reset level settling. vertical row scanner and its programability, timing sequenser 60 fps read out, timing sequenser work with column ADC. timing. Designed Unit Cell.\\\\nBring up several dual mode MWIR/LWIR ROICs post silicon debuging and troubleshoot ing, Root cause analysis.\\\\nSupervise layout designer for Analog ROIC layout library creation.\\\\nWriting proposal for DARPA for future universal analog front area which will work for oR LWIR/MWIR visible UV inputs together with TOF LIDAR as linear as Geiger mode.\\\\nDesign bandgap and current reference.\\\\nStress analysis of flying probe data for PCB assembly. PCB circuits for EO Space and Sensors and IMS \\\\n \\\\n\\\\n \\\\n \\\\n\\\\n \\\\n

Education

• IEEE ISSCC 2016

  Engineer’s Degree, ADVANCED ULTRA HIGH SPEED WIRELINE TRANSCEIVERS

  2016 — 2016

• New Jersey Institute of Technology

  Master of Science (MS), Electrical and Electronics Engineering

  1996 — 1998

• L3Harris training

  Diploma, Infrared camera systems

• TEXAS INSTRUMENTS TECHNICAL UNIVERSITY

  12 credit hours, advanced VLSI design

  2000 — 2001

• New Jersey Institute of Technology, Newark, NJ, USA.

  MS. EE, Electronics Engineering

  1996 — 1998

• GLOBAL FOUNDRIES training

  7nm FiNFET expert, 7nm 7LPP process layout and CAD

  2016 — 2016