Alex Levenzon
- Role
- Senior Physical Design Engineer at Intel
- Location
- Portland, OR, US
- LinkedIn followers
- 500 followers
About Alex Levenzon
Experienced Circuit/BE design Engineer/Technical Leader • Extensive hands-on…
Experience
Senior Physical Design Engineer
Jan 2021 — Present
CPU design team – partition PNR + Designed high complexity, timing critical partition in the CPU core, using Synopsys tools (Fusion compiler) and Cadence tools (Genus / Innovus).+ Defined methodology for improving efficiency of collaborative work with FE RTL team in analyzing of critical timing paths and testing of corresponding RTL fixes.+ Led multiple floorplan exploration studies to find highly efficient partition floorplan and to achieve timing convergence of the block.
Skills
- Processors
- Synopsys Tools
- Systemverilog
- Low-Power Design
- Microprocessors
- Physical Design
- Logic Design
- Debugging
- Logic Synthesis
- Analog Circuits
- Soc
- Tcl
- Rtl Design
- Drc
- Asic
- Analog
- Verilog
- Semiconductors
- Circuit Design
- Vlsi
- Static Timing Analysis
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