Alekhya Polapally
Design Verification Engineer | ASIC | SoC | PCIe | CXL
- Role
- Design Verification Engineer at MosChip®
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Alekhya Polapally
Good knowledge of Digital Design Concepts and Proficient in Verilog HDL, System Verilog…
Experience
Design Verification Engineer
Aug 2022 — Present · Hyderabad, IN
Currently working on PCIe and CXL protocols in a high processor computer architecture, need to verify the IP level testcases for PCIe and CXL protocols.previously worked on PCIe TL layer testbench and complete architecture, also worked on SPI, Ethernet and AMBA APB
Education
Bhojreddy engineering college for women
Bachelor's degree
2018 — 2022
Sri Chaitanya junior college Hyderabad
Intermediate
2016 — 2018
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