Alan Ryan

Ic Consultant (Dft) @Ensilica

Wokingham, GB

From starting as a consultant and later assuming a permanent position as DFT lead at Ensilica I have developed EnSilica’s DFT competence by insisting on the adoption of best practice, incorporating the latest advances in EDA tooling into our flows and mentoring graduate engineers. Working and communicating closely with customers, project managers, operations engineers, analog design engineers, physical design engineers and frontend engineers I have had the pleasure of seeing the company increase its ability to deliver high quality designs to stringent requirements with limited time and resources.• Running a small but busy DFT department including recruitment, mentoring engineers, advising clients, keeping our DFT flow up to date and dealing with multiple live projects.• Defining. recommending and implementing DFT architectures, generating DFT specifications, DFT insertion and verification.• TAP, Boundary Scan and IJTAG Network insertion and verification.• Scan Coverage analysis and design optimisation recommendations for coverage enhancement.• ATPG Scan Compression and OCC insertion. Test Point Insertion.• Memory BIST insertion, verification, and pattern generation.• Scan pattern generation, verification, and validationo Stuck-at, CAT, Transition, IDDQ, Bridge, Path Delay• Test mode entry and exit, low pin count test, optimisation for multiple IC package configurations.• Design to incorporateo Power and physical constraints including IR drop, power, and voltage domains.o Flat vs. Hierarchical testo Physical routing constraints, and pin placement.• DFT Timing constraints development and debug.• Analog IP and subsystem modelling, test development and test implementation.• ATE and or validation-based Test Pattern debug and diagnostics.

Universidad Politécnica de Madrid

MEng, Electronics, Maths, Spanish

The University of Manchester

MEng (1st Class), Electronic Systems Engineering