Akshay Kunder

About Akshay Kunder

Electrical Engineering graduate in the field of ASIC Design & Verification, currently working at Intel as Senior Validation Engineer,Subject Expertise:• MS Electrical Engineering with specialization in ASIC Design & Verification and around 7+ years of industry experience.• Experience of RTL design, ASIC gate level synthesis and FPGA prototyping.• Experience of creating verification plan, UVM test bench from scratch, constraint random and directed test cases and SV Assertions. • Knowledge of Static Timing Analysis, clock domain crossing (CDC) and DFT techniques like BIST, scan chain. • Experience of Object Oriented Programming (SV), scripting language (Perl), C prog.• Worked on design & verification of CPU RISC architecture and DSP image processing related projects.• Experience of building industry level Floating Point Co-processor unit like FMA, FFT and MatMul and Encryption Engine designs.• EDA Tools: Synopsys VCS, Xilinx ISE Design Suite, Cadence NC-Verilog Simulator, Quartus 2 - ModelSim, Questa Sim• Operating Systems: Windows, Linux, UNIXContact:Email: a••••••••@gmail.comPhone:+16•••••••56

Experience

1. Senior Ip Design Verification Engineer

   Intel

   Mar 2022 — Present · Santa Clara, CA, US

   Part of the Scalable Fabric Validation team responsible for the pre-silicon verification of the different generations of the Scalable Fabric IP for Intel\'s NextGen products.

Education

• North Maharashtra University

  Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering

  2009 — 2012

• San José State University

  Master’s Degree, Electrical Engineering

  2015 — 2016

Skills

• Sql
• Linux
• Microsoft Office
• Questasim
• C
• Programming
• Systemverilog
• Microsoft Excel
• Business Intelligence
• Xilinx Ise
• Sdlc
• System Verification
• Pl/Sql
• Uvm
• Perl
• Requirements Analysis
• Java Enterprise Edition
• Functional Verification
• .net
• Microsoft Bi Suite
• Microsoft Sql Server
• Fpga
• Verilog
• C++
• Code Coverage