Akshay G
Senior Memory Design Engineer at Arm
- Role
- Senior Design Engineer at Arm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Senior Design Engineer
Mar 2018 — Present · Bengaluru, IN
Education
Sadvidya Composite PU College, Mysore
2nd PUC, PCME
2004 — 2006
Vidya Vardhaka College of Engineering, Mysore (Affiliated to VTU, Belgaum)
B.E, Electronics and Communication Engineering
2006 — 2010
Ideal Jawa Rotary High School, Mysore
10th
2001 — 2004
Skills
- Memory Circuit Design
- Systemverilog
- Drc
- Lvs
- Simulations
- Memory Leaf Cells Layout
- Shell Scripting
- Verilog
- Sram Memory Design
- Layout Tools
- Design Rule Checking (Drc)
- Sram
- Digital Circuit Design
- Vlsi
- Memory Characterization
- Asic
- Circuit Design
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