Akshaya Anand
IP Logic Design Engineer at Intel Corporation
- Role
- Ip Logic Design Engineer at Intel
- Location
- Kollam, IN
- LinkedIn followers
- 500 followers
About Akshaya Anand
I completed my Masters in VLSI and currently working as a Full time IP Logic Design engineer in the Thunderbolt Department at Intel Corporation. Knowledge of RTL design using Verilog 2. Basic experience in debugging IP design failures by use of static verification tools (Intel tools : VISA, Collage; Synopsys tools: LINT, CDC, RDC, VCLP; Fishtail). Knowledge on Automation scripting based on Perl, UNIX/LINUX shells.
Experience
Ip Logic Design Engineer
Aug 2022 — Present · Bengaluru, IN
Education
Mount Carmel Convent School - India
High School, Science, 9.2
2014 — 2016
Sri Krishna College of Engineering and Technology
Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering, 8.9
2016 — 2020
AMRITA VISHWA VIDYAPEETHAM
Master of Technology - MTech, VLSI, 9.35
2020 — 2022
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