Akshaya V

About Akshaya V

ASIC Design Verification Engineer with 4+ years of experience in IP and SoC-level verification.Capable individual with a master\'s degree in VLSI Design, intending to use acquired academic knowledge and demonstrated technical skills with solid grasp of digital design ideas, fundamentals of transistors, verilog HDL coding, and VLSI design flow. A solid understanding of System Verilog principles and Design Verification. Possess a basic understanding of C programming. Possess practical knowledge in software tools such as Cadence, Synopsys VCS, Questasim, etc. Implemented VLSI tasks while in the post-graduate stage, and an article was published.

Experience

1. Senior Vlsi Engineer

   Wipro

   Aug 2025 — Present · IN

Education

• Saintgits College of Engineering, Kottukulam Hills, Pathamuttam P.O., Kottayam 686532

  Bachelor's degree

  2014 — 2018

• AMRITA VISHWA VIDYAPEETHAM

  Master's degree

  2018 — 2020