Akshay Thota

About Akshay Thota

I am a results-driven and highly motivated VLSI Physical Design Engineer and a masters graduate from Electrical & computer engineering with deep hands-on experience driving designs from RTL to GDSII for performance-critical ASIC blocks. I thrive at the intersection of timing, power, and physical implementation, and I enjoy solving complex design challenges that directly impact silicon quality, performance, and reliability. Some of my notable work includes:I bring a strong problem-solving mindset to: 1. Timing closure across all corners and modes. CTS optimization for skew, latency, and clock quality. Congestion mitigation and routing optimization. EM/IR, signal integrity, antenna, and reliability analysis. DRC/LVS/ERC clean physical signoff. Expertise in floorplanning, clocking, and power network architecture, resulting in optimal chip performance and power efficiency. Implemented low-power design using UPF power intent flow, minimizing power consumption without compromising performance. Conducted LVS, DRC, ERC, EMIR (static & dynamic), LEC, and Reliability sign-off checks to ensure design robustness. I am always eager to learn new advanced-node methodologies, low-power techniques, and automation strategies to improve design quality and efficiency. Open to contributing on high-impact ASIC / SoC projects where performance, quality, and engineering excellence truly matter.

Experience

1. Physical Design Engineer

   Broadcom

   Sep 2024 — Present · San Jose, CA, US

   Delivered 3 advanced-node blocks (5nm) from netlist to GDSII, achieving 0 WNS and full MCMM signoff closure at 3.8–4.0 GHz target frequency.• Handled Placement & Routing (PnR) using industry-standard EDA tools, resolving congestion and routing bottlenecks.• Executed Static Timing Analysis (STA) using Primetime (PT/PT-SI), improving WNS/TNS and achieving target frequency goals.• Collaborated with RTL, synthesis, DFT, and top-level SoC teams to align constraints, clock assumptions, and timing models.• Performed clock tree synthesis (CTS) analysis, addressing skew, latency, and reconvergence issues to maintain timing margins.• Conducted IR drop, EM, and signal integrity analysis, coordinating fixes using tools like RedHawk to protect worst-case timing paths.• Automated STA and ECO workflows using Tcl and Python scripting, reducing manual debugging time by 30%.• Ensured signoff-quality delivery, running DRC/LVS and regression checks before tape-out.• Supported advanced-node migration (5nm to 3nm) by updating automation scripts and validating new metal stacks and hybrid track configurations.• Performed SPICE-level validation for critical paths, correlating STA results with transistor-level simulations.• Documented timing closure strategies and debug methodologies for 5 blocks, cutting reuse ramp-up time by 40% across 3 future programs and reducing violations by 25% in initial implementations.

Education

• Southern Illinois University, Carbondale

  Masters in electrical and computer engineering

• SR Engineering College

  Bachelor of Engineering - BE, Electrical and Electronics Engineering

  2016 — 2021