Akshay Sridharan

About Akshay Sridharan

Akshay Sridharan joined NVIDIA as a Senior Power ASIC Engineer in December of 2015. Prior to joining, he received his PhD from University of Texas at Dallas, where his research focused on low power asynchronous and sub-threshold digital circuit design. At NVIDIA, he has been part of the GPU power methodology team where he is responsible for developing and maintaining gate level simulation, SPICE simulation, power estimation flow, and glitch power reduction.

Experience

1. Sr Power Asic Egineer

   NVIDIA

   Jan 2016 — Present · San Francisco, CA, US

   Architect of NVIDIA\'s GPU accelerated Power estimation flow• Custom and EDA power tools (PTPX/PowerArtist) methodology implementation and power estimation support for unit and IP teams on NVIDIA GPUs.• Methodology and support for internal power tracking web-based tools.• Power estimation for physical design at partition level• Glitch power estimation and reduction techniques.• SPICE power correlation.• Power budgeting and driving reduction with architectural teams• RTL/Gate level power estimation and reduction.

Education

• The University of Texas at Dallas

  Doctor of Philosophy (Ph.D.), Electrical and Electronics Engineering

  2012 — 2015

• The University of Texas at Dallas

  masters of Science, Electrical Engineering

  2011 — 2013

Skills

• Labview
• Verilog
• Pspice
• C
• Digital Signal Processing
• Vlsi
• Html
• Microcontrollers
• Cmos
• Application-Specific Integrated Circuits (Asic)
• Windows
• Field-Programmable Gate Arrays (Fpga)
• Cadence Virtuoso
• Embedded Systems
• Digital Signal Processors
• Analog Circuit Design
• Circuit Design
• Integrated Circuit Design
• Matlab
• Low-Power Design
• Logic Design
• Testing
• Very-Large-Scale Integration (Vlsi)
• Electrical Engineering
• Signal Processing
• Simulink
• Analog Design
• Rtl Design
• Spice
• Embedded C
• C++
• Digital Electronics
• Xilinx Ise
• Synopsys Tools
• Linux
• Modelsim
• Electronics
• Unix
• Fpga
• Asic