Akshay Shinde
Manager at AMD
- Role
- Manager Silicon Design Engineering at AMD
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Akshay Shinde
7 years of experience in design and verification-Excellent debugging skills-Experienced in design and development work in verilog technologies -Testbench and testplan development using UVM and system verilog-Worked on North Bridge IP-Worked on coverage driven verification-Worked on Ethernet, AXI, AHB, APB, SPI protocols-Good team player Programming Languages : Verilog, System Verilog, UVM Domain knowledge : Ethernet, AXI, AHB, APB, SPI (serial peripheral Interface), MOESI Front-end design : Processor and NB IP verification, Debugged the complex architectures, Working knowledge in digital design and Algorithm, Microarchitecture, Functional verification and coverage. Tools : mpSim (Axiom), VCS, ncverilog Bug tools : bugzilla, jira Platforms : Linux, Windows
Experience
Manager Silicon Design Engineering
Jul 2023 — Present
Skills
- Uvm
- Functional Verification
- Debugging
- Digital Designs
- Logic Synthesis
- Soc
- Verilog
- Rtl Coding
- Asic
- Vlsi
- Systemverilog
- Vhdl
- Microarchitecture
- System Verilog
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