Akshay S.
ASIC Design Verification Staff R&D Engineer @ Synopsys | Silicon IP | Verification IP | UVM | SV | SVA |
- Role
- Staff Verification Engineer R & d Engineering at Synopsys Inc
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Akshay S.
Experienced Design Verification Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Universal Verification Methodology (UVM), SystemVerilog, Silicon Pre-Validation/Verification Engineering. Test bench bring up in IP, NoC, SoC, & CPU sub-system verification. Currently working on Design Verification of IP (MIPI Unipro + MIPI MPHY) using SystemVerilog/UVM testbenches.Hands on ExperienceProtocols: AMBA Family: • CHI, AXI-AXI5/LITE, ACE5/LITE, AXI4STREAM, AXI3/4/LITE • AHB-AHB2, AHB5, AHB-Lite. • APB-APB2/3/4; MIPI Family: Unipro, MPHYSimulator and Tool: VCS, VERDI, DVEVerification Languages: SystemVerilog, Verilog.Methodology: UVM, OVM
Experience
Staff Verification Engineer R & d Engineering
Jan 2025 — Present · Hyderabad, IN
Education
R. V. College of Engineering, Bangalore
Master's degree, VLSI & Embedded Systems
2017 — 2019
JSS Academy of Technical Education
Bachelor's degree, Electrical, Electronics and Communications Engineering
2013 — 2017
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