Akshay Rastogi
Sr. Design Engineer @Qualcomm Camera team, Multimedia Group || CDAC Pune Alumni
- Role
- Senior Design Engineer at Qualcomm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Akshay Rastogi
With 4+ years of experience in VLSI domain with exceptional skills in RTL Design, Lint and CDC check, looking for a challenging role in organisation pushing the frontiers of next-generation technology. Passionate to learn more and apply more.Skills:• Hardware Skills : RTL Design, Timing closure, Lint, CDC, Systemverilog Assertion.• Programming Languages : Verilog, Systemverilog, VHDL, C/C++, Tcl, Perl, Shell Scripting.• Tools : Xcelium, Genus, Xilinx Vivado„ Xilinx ISE, Questa Sim, Questa Formal, Spyglass.• Protocols : SPI, AXI, NIC, PCIe
Experience
Senior Design Engineer
Oct 2022 — Present · Bengaluru, IN
Education
Bhagwant University, Ajmer
B.Tech, Electronics & Communication Engineering
2011 — 2015
Centre for Development of Advanced Computing (C-DAC)
Post Graduation Diploma in VLSI, Digital Design, VHDL, Verilog, System Verilog, UVM
2018 — 2018
S.G.M. INTER COLLEGE KANPUR, UTTER PRADESH
Intermediate, Physics, chemistry and Maths
2008 — 2010
Skills
- Matlab
- Troubleshooting
- Planning
- C++
- C
- Windows
- Microsoft Excel
- Powerpoint
- Project Management
- Customer Service
- Public Speaking
- Leadership
- Microsoft Office
- Microsoft Word
- Analysis
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