Akshay Raj

About Akshay Raj

First and foremost, I loved coding, ever since I wrote my first code in C. It is always fun and challenging writing test bench in system verilog. Good experience in writing RTL models using Verilog HDL and also verifying them using UVM. Knowledge in Assertion Based Verification(ABV). 4.Worked on lint and CDC in spyglass. My areas of interest include RTL design, Verification, SOC and ASIC design. VLSI domain skills: HDL - VHDL, Verilog HDVL - System Verilog Verification Methodologies: Coverage Driven Verification, Assertion Based Verification - SVA, UVM EDA Tools: Vivado, Xilinx ISE, EDA Playground

Experience

1. Rtl Design Engineer

   L&T Technology Services

   Feb 2022 — Present · Hyderabad, IN

Education

• Bapuji Institute of Engineering & Technology, DAVANAGERE

  Bachelor of Engineering - BE, Electronics and communication engineering

  2015 — 2019

• Keshava Reddy Concept School

  SSC