Akshay Rai
Silicon Engineer at Google | ASIC Physical Design and Implementation
- Role
- Senior Silicon Physical Design Engineer at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Akshay Rai
Senior Silicon Physical Design Engineer with over 10 years of industry experience. Worked with some of the top semiconductor firms. During my professional journey so far, I was involved in taping out the blocks for graphics, CPU, accelerators and ethernet SoCs. I have done block level design for many key products, some of them (not limited to) are- Google Tensor- Latest gen ARM CPU cores- Serdes- Latest gen Intel graphics- Tensor SoC- Low power CPU cores- AMD CPU core.Skills:• Place and route.• Synthesis• Static timing analysis.• EM/IR.Responsibility - Driving convergence of multi-million gate count block for the best PPA and DRCs.
Experience
Senior Silicon Physical Design Engineer
Nov 2024 — Present · Bengaluru, IN
Tensor SOC - Multimedia
Education
Rajiv Gandhi Prodyogiki Vishwavidyalaya
Bachelor of Engineering (BE), Electronics and Communications Engineering
2009 — 2013
Kendriya Vidyalaya
SSC
Sri Chaitanya College of Education
HSC
Vellore Institute of Technology
Master's degree, VLSI Design
2014 — 2016
Skills
- Front-End Design
- Perl
- Application-Specific Integrated Circuits (Asic)
- Soc
- Physical Verification
- Functional Verification
- Signal Integrity
- Front-End Coding
- Digital Ic Design
- Formal Verification
- Tcl
- Rtl Verification
- Field-Programmable Gate Arrays (Fpga)
- Verilog
- Fpga
- Low-Power Design
- Asic
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