Akshay Patharkar
System-on-Chip Design Engineer at Intel Corporation
- Role
- System-on-chip Design Engineer at Intel
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
About Akshay Patharkar
Two plus years of working experience in Intel Bangalore as a Front End Design engineer. Currently involved in writing SoC level as well as IP level UPF and running low power linting tools such as VCLP. Also working on RTL integration related work. Holds an M.Tech degree focused on Integrated Electronics and Circuits (VLSI) from VIT, Vellore and B.E Electrical from Pune University.
Experience
System-on-chip Design Engineer
Jul 2020 — Present · Bengaluru, IN
Front End Design engineer for Intel\'s server processor group. Duties include but are not limited to- Designing UPF for server processors, IPs etc - Running Static low power checks using VCLP - RTL integration related work
Education
Fergusson College
HSC, Science
2010 — 2012
Bhausaheb Firodiya High School
Ssc, School
2005 — 2010
University of Pune
BTech - Bachelor of Technology, electrical engineering, 8.2
2013 — 2017
Vellore Institute of Technology
Master of Technology - MTech, VLSI DESIGN, 8.75
2018 — 2020
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