Akshay Deole
Lead Design Engineer at Cadence
- Role
- Lead Design Engineer at Cadence
- Location
- Pune, MH, IN
- LinkedIn followers
- 500 followers
About Akshay Deole
Working on the serdes IP ranging from 10Gbps to 56Gbps on 40nm, 16nm, and lower technology node-Experienced Analog Circuit Design Engineer with a demonstrated history of working in the semiconductors industry-Worked on the designing of different type of amplifiers-Single stage, Differential, Opamps such as Floded-Cascode, Telescopic Cascode etc, Crystal Oscillator, PLL, VCOs, LDOs (Low Dropout Regulator), Bandgap Reference, Frequency Divider, Charge Pump, Phase-Frequency Detector, Level Shifter, Biasing circuits-Having very good knowledge on a transistor-level design, practice and experience in different technology node such as TSMC-40nm, GF-22nm, 45nm, 55nm-Tools & Languages: Cadence virtuoso, Verilog-A
Experience
Lead Design Engineer
Dec 2022 — Present · Pune, IN
Education
COEP Technological University
Master of Technology (M.Tech.)
2016 — 2018
SSGMCE,Shegoan
B.E
2011 — 2015
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