Akshay Bhat

Senior Functional Safety Engineer @Arm

Munich, DE

EMAILS

[email protected]

MOBILE NUMBERS

+91 *********19

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WORK HISTORY

Apr 2026 — Present

Senior Functional Safety Engineer @Arm

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Munich, DE

EDUCATION

2014 — 2016

HSB Hochschule Bremen – City University of Applied Sciences

Master of Science (M.ScEE.), Microsystems Engineering

SKILLS

System on a Chip (Soc)Software DevelopmentPythonUniversal Verification Methodology (Uvm)C++MicrocontrollersIntegrated Circuits (Ic)System VerificationCadence VirtuosoEmbedded SystemsEdaSocSystem on Chip (Soc)CadenceIcMicrofabricationSystemverilogQuestaVhdlSimulationsSapApplication-Specific Integrated Circuits (Asic)Mixed-Signal Ic DesignVerilogElectronicsMicrosoft ExcelCProgrammingMicrosoft OfficeMicrostructureLinuxMixed SignalFunctional VerificationSemiconductorsMatlabSystem Verilog(Xilinx)Hardware Architecture

ABOUT AKSHAY BHAT

Functional Safety Architect centers around enhancing the safety and reliability of semiconductor systems. Expertise in developing safety architectures and implementing safety standards like ISO 26262 and IEC61508. The transition from SoC Verification Engineer to Safety Architect leveraged my deep understanding of SOC design, safety functions and architecture, specifically within the automotive and Industrial SoCs. Collaborating with dedicated teams, we\'ve achieved significant milestones in bringing safe and secure application processors to market. Our work contributes to the important goal of creating fail-safe systems in an era where digital infrastructure becomes increasingly critical.

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