Akshay Adlakha
Analog Design Manager at Synopsys | SerDes (PAM4, 112G/PCIe7) | Low jitter PLLs and clocking | Masters in Electrical Engineering IIT Bombay
- Role
- Analog Design Manager at Synopsys Inc
- Location
- Boston, MA, US
- LinkedIn followers
- 500 followers
About Akshay Adlakha
Analog Design Manager at Synopsys Inc.Leading a global design team for high speed (100+G) PAM4 SerDes products.Core Competencies:SerDes (PAM4, 112G/PCIe7)| Low-Jitter PLLs (analog/digital)| Clocking Solutions (DLL/ILOs, low jitter clock distribution, phase rotators)| Power Management (LDO, bandgaps, DVS)| Lab Debug & Characterization | Global Team Leadership
Experience
Analog Design Manager
Apr 2022 — Present · Boston, MA, US
Education
Indian Institute of Science (IISc)
Master of Technology (MTech) (partial completion), Aerospace Engineering
2013 — 2014
Indian Institute of Technology, Bombay
Master of Technology (M.Tech.), Electronic Systems
2014 — 2016
Delhi Public School - R. K. Puram
12th Board, Science
2007 — 2009
Guru Gobind Singh Indraprastha University
Bachelor of Technology (BTech), Electronics and Communication Engineering
2009 — 2013
Salwan Public School
10th Board
2007
Skills
- Microsoft Word
- Modelsim
- Cadence Virtuoso
- Programming
- Vlsi
- Public Speaking
- Microsoft Excel
- Research
- Mentor Graphics
- Altera Quartus
- Cadence Spectre
- Code Composer Studio
- Matlab
- C++
- English
- Latex
- Analog
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.