Akshatha M
PCB and IC package engineer | Silicon Package Design Engineer @ Intel Corporation | BE in Electronics Engineering
- Role
- Silicon Package Design Engineer at Intel
- Location
- Mysuru, IN
- LinkedIn followers
- 500 followers
About Akshatha M
As a Silicon Package Design Engineer I strive to deliver comprehensive IC package…
Experience
Silicon Package Design Engineer
Jul 2022 — Present · Bengaluru, IN
Led end-to-end package design for high-performance digital and mixed-signal ICs used in computing and communication products. Experience in substrate layout of flip chip packagesDelivered 14+ package design tape-outs with complete ownership from concept to manufacturing handoff.Delivered the design from scratch to the Tape-Out, including Ballmap planning, SI/PI Review, Constraint setup, Gerber Review, and Vendor Collateral review. Worked on package design including feasibility studies, substrate design/routing, package stack up.Delivered DDR & PCIe substrate designs ensuring compliance with SI/PI metrics and enabling successful tape-out.Collaborated with cross-functional stakeholders to define package specifications and performance targets.Conducted comprehensive thermal, mechanical, and electrical simulations to optimize package performance and reliability.Trained peers on loopback design concepts and enhanced review methods to strengthen power integrity checks.
Education
Sadvidya pre-university college
Pre-University, Electronics
2016 — 2018
Vidyavardhaka College of Engineering
Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering
2018 — 2022
Birla Institute of Technology and Science, Pilani
Master of Technology - MTech, VLSI design and Microelectronics
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